Senior Engineer II - APID Digital Design
To be part of a global organisation with a strong brand presence
Attractive remuneration packages
About Our Client
My client is a public-listed, multinational corporation in the Electronics & Semiconductor industry. With a strong global presence across numerous countries, my client's deep-rooted expertise has definitely propelled them to be a key player within the industry. Interested to be part of the team? Apply now!
- Read and understand engineering documents for digital blocks and mixed-signal systems.
- Architecture and RTL coding of digital circuits.
- Writing block level Verilog/System-Verilog directed test-benches and supporting verification team with debug.
- Perform synthesis, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (10K to 200K+ gates) which are coded in Verilog.
- Work with local or remote project lead to meet timing closure, area, power, and performance requirements for macro under development.
- Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
- Communicate regularly with the local or remote project lead to resolve issues and to ensure meeting targeted goals and schedule.
The Successful Applicant
- Degree in Electronic/Electrical or Computer Science
- At least 5 Years of Experience in ASIC Development
- Understand Design-For-Test concepts and methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation).
- Understand and experienced with logic timing requirements (setup/hold/uncertainties)
- Scripting skills in any programming language (preferably Perl, TCL and Shell) is a plus.
- Experienced in RTL coding and synthesis concepts.
What's on Offer
- To be part of a global organisation with a strong brand presence
- Attractive remuneration packages
- Opportunity to learn, grow and succeed within the business